ECE519(00)  Microprocessor Microarchitecture

▣ Lecture outline


  Traditional speedup curve of Amdahl's law no longer applies to computer system performance. All the recent high-performance designs of Intel, IBM, and Sun rely on multi-core technology. This technical shift from ILP (instruction-level parallelism) to TLP (thread-level parallelism) will reshape the design of future microprocessors. In this course, we will cover both ILP and TLP techniques. The topics we cover include adaptive dynamic branch prediction, high-bandwidth instruction fetch, dynamic scheduling, multiple issue, speculation, multithreading, symmetric multiprocessors, distributed shared memory multiprocessors, synchronization and consistency, and cache and memory hierarchy designs.

 Professor : Lynn Choi( lchoi@korea.ac.kr, Engineering Bldg, #411, 3290-3249)

 Assistant : WonJoon Son(swj8905@korea.ac.kr, Engineering Bldg, #236, 3290-3896)

 Time(Place) : Wednesday(1-2) WooJung information & communications Building #B103

 Textbook : "Computer Architecture: A Quantitative Approach", John L. Hennessy and David A. Patterson, Morgan Kaufmann, 5th Edition, 2012

 Reference book : A Collection of Research Papers

▣ Bulitin Board : http://it.korea.ac.kr/engine/index.php?mid=class_notice

 Class notice




1. Lecture Note 1 was updated on March 5.

2. Lecture Note 2 was updated on March 13.

3. Reading List was updated on March 20.

4. Lecture Note 3 was updated on March 26.

5. Lecture Note 4 was updated on April 2.

6. Lecture Note 5 was updated on April 10.

7. Lecture Note 6 was updated on April 30.

8. Lecture Note 7 was updated on April 30.

9. Lecture Note 8 was updated on May 8.


▣ Lecture slide


1. Microarchitecture_-_0._Introduction[4128].pdf

2. Microarchitecture_-_1._Branch_Prediction.pdf

3. Microarchitecture_-_2._Instruction_Fetch[4193].pdf

4. Microarchitecture_-_3._Dynamic_Pipeline.pdf

5. Microarchitecture_-_4._Interrupt_and_Precise_Exception.pdf

6. Microarchitecture_-_5._Memory_Hierarchy_Optimization.pdf

7. Microarchitecture_-_6._Limits_of_ILP.pdf

8. Microarchitecture_-_7._Thread_Level_Parallelism.pdf


▣ Reference


 Paper Presentation



Presentation List

김건호 - 1. Prediction based Execution on Deep Neural Networks (ISCA, 2018)

             2. Eyeriss: A Spatial Architexture for Energy-Efficient Dataflow for Convolutional Neural Networks (ISCA, 2016)

권기용 - 1. Criticality Aware Tiered Cache Hierarchy:A Fundametal Relook at Nulti-Level Cache Hierarchies (ISCA, 2018)

이훈재 - 1. Continuous runahead: transparent hardware acceleration for memory intensive workloads (MICRO, 2016)

             2. Charge Cache : Reducing DRAM Latency by Exploiting Row Access Loocality (HPCA 2016)

이준연 - 1. BranchScope: A New Side-Channel Attack on Directional Branch Predictor (ASPLOS, 2018)

김동재 - 1. A Hardware Accelerator for Tracing Garbage Collection (ISCA, 2018)

김정현 - 1. Fused-layer CNN accelerators (MICRO, 2016)

              2. E-RNN: Design Optimization for Efficient Recurrent Neural Networks in FPGA (HPCA, 2019)

고영웅 - 1. UCNN:Exploiting Computional Reuse in Deep Neural Networks via Weight Repetition (ISCA, 2018)
             2. Gist:Efficient Data Encoding for Neural Network Training (ISCA, 2018)

노인성 - 1. SCALE DEEP:A Scalable Compute Architecture for Learning and Evaluating Deep Networks (ISCA, 2017)

             2. A Configurable Cloud-Scale DNN Processor for Real-Time AI (ISCA, 2018)


김채영 - 1. Cambricon-S: Addressing Irregularity in Sparse Neural Network through A Cooperative Software/Hardware

                Approach (MICRO, 2018)

              2. ComPEND: Computation Pruning through Early Negative Detection for ReLU in a Deep Neural Network

                Accelerator (ICS, 2018) 

황병진 - 1. A Many-core Architecture for In- Memory Data Processing (Micro, 2017)
             2. Architectual Support for Probabilists Branches (Micro, 2018)



 Reading List