ECE519(00) Microprocessor Microarchitecture
▣ Lecture outline
|Traditional speedup curve of Amdahl's law no longer applies to computer system performance. All the recent high-performance designs of Intel, IBM, and Sun rely on multi-core technology. This technical shift from ILP (instruction-level parallelism) to TLP (thread-level parallelism) will reshape the design of future microprocessors. In this course, we will cover both ILP and TLP techniques. The topics we cover include adaptive dynamic branch prediction, high-bandwidth instruction fetch, dynamic scheduling, multiple issue, speculation, multithreading, symmetric multiprocessors, distributed shared memory multiprocessors, synchronization and consistency, and cache and memory hierarchy designs.|
▣ Professor : Lynn Choi( email@example.com, Engineering Bldg, #411, 3290-3249)
▣ Assistant : HanJun Bae(firstname.lastname@example.org, Engineering Bldg, #236, 3290-3896)
▣ Time(Place) : Monday(6-8) West Building, College of Life Sciences & Biotechnology, #103
▣ Textbook : "Computer Architecture: A Quantitative Approach", John L. Hennessy and David A. Patterson, Morgan Kaufmann, 5th Edition, 2012
▣ Reference book : A Collection of Research Papers
▣ Bulitin Board : http://it.korea.ac.kr/engine/index.php?mid=class_notice
▣ Class notice
1. Lecture Note 1 was updated on March 2.
2. Lecture Note 1 was updated again on March 5.
3. Lecture Note 1 was updated again on March 6.
4. Lecture Note 2 was updated on March 12.
5. Lecture Note 3 was updated on March 12.
6. Reading List 1 was updated on March 13.
7. Lecture Note 2 was updated again on March 20.
8. Lecture Note 4 was updated on March 26.
9. Lecture Note 5 was updated on March 31.
10. Lecture Note 6 was updated on April 8.
11. Lecture Note 7 was updated on April 17.
12. Lecture Note 8 was updated on May 1.
13. Lecture Note 9 was updated on May 7.
14. Lecture Note 9 was updated again on May 14.
※ 강의 시간(16:00 으로 최종 변경되었습니다.)
강의 장소(생명과학관 동관 104호로 최종 변경되었습니다.)
※ 5월 22일 수업은 15:30 으로 변경되었습니다.
※ 선정된 논문 List
2. Future Vector Microprocessor Extensions for Data Aggregations
3. Back to the Future : Leveraging Belady's Algorithm for Improved Cache Replacement
4. Efficient Synonym Filtering and Scalable Delayed Translation for Hybrid Virtual Caching
5. APRES : improving cache efficiency by exploiting load characteristics on GPUs
2. SABRes Atomic Object Reads for In-Memory Rack-Scale Computing
3. pTask : A Smart Prefetching Scheme for OS Intensive Applications
4. Towards Efficient Server Architecture for Virtualized Network Function Deployment_Implications
Qos Guarantee(Arizona State University)
2. Energy-Efficient Address Translation A Graph-Based Program Representation for Analyzing
Hardware Specialization Approaches
3. Predicting the Memory Bandwidth and Optimal Core Allocations for Multi-threaded Applica-
1. Doppelganger: A Cache for Approximate Computing
1. A VariableWarp Size Architecture
1. Msacar : Speeding up GPU Warps by Reducing Memory Pitstops
▣ Lecture slide
▣ Paper Presentation
▣ Reading List