Early registration is extended to August 5th, 2007!

ACSAC 2007
The 1st CFP has been announced !

The paper submission is extended to April 12th 19th, 2007

Advanced registration is open. Due date is 20th June.

Advance Program of the Conference is now available as of June 25th, 2007!


Conference Banquet/Tour Information is now available as of August 24th, 2007!

On-line proceedings are available.

Conference photo is available.

  Call for Participation

 

 

 

 

 

 

Advance Program


 Time 
 Wednesday, August 22 
 Thursday, August 23 
 Friday, August 24 
 Saturday, August 25 
 8:45~9:00 
 
 Welcome 
 
 
 9:00~10:00 

 Keynote I 
 
 Keynote II 
 Session 7 
 9:00~9:50 
 10:00~10:25 
 
 Break 
 10:25~12:30 

 Session 1 
 
 Session 4 
 Session 8 
 10:20~12:00 
 12:30~14:00 
 Tutorial 
(13:00 ~ 18:00)
 Lunch 
 Closing 
 14:00~16:05 

 Session 2 
 
 Session 5 
 
 16:05~16:30 
 Break 
 
 16:30~18:10 

 Session 3 
 
 Session 6 
 
 19:00~21:00 
 
 Executive Meeting 
 Conference Banquet 
 
 21:00~23:00 
 
 
 Conference Tour 
 
 Location Informaion 
 Hana Square Multimedia Room 
 Hana Square Auditorium 

Conference Banquet Information
Conference Tour Information


DAY 1
Tutorial

 Compilation and Software Development Challenges in the Multicore Era (1:00~6:00 )

 Partha tirumalai and Yonghong Song  [ Abstract ]   

DAY 2
Keynote

 A Compiler Framework for Supporting Speculative Multicore Processors (9:00~10:00 )

 Pen-Chung Yew   [ Abstract ]   [ Bio ]
 
 1 
  Static and Dynamic Program Optimization (10:25~12:30 )
 Session Chair : Yonghong Song (Sun Microsystems)

 StarDBT: An Efficient Multi-Platform Dynamic Binary Translation System
 Cheng Wang, Shiliang Hu, Ho-seop Kim, Sreekumar Nair, Mauricio Breternitz, Jr., Zhiwei Ying, Youfeng Wu

 Unbiased Branches: An Open Problem
 Arpad Gellert, Adrian Florea, Maria Vintan , Colin Egan , Lucian Vintan

 An Online Profile Guided Optimization Approach for Speculative Parallel Threading
 Yuan Liu, Hong An, Bo Liang, and Li Wang

 Entropy-Based Profile Characterization and Classification for Automatic Profile Management
 Jinpyo Kim, Wei-Chung Hsu, Pen-Chung Yew, Sreekumar R. Nair, Robert Y. Geva

 Laplace Transformation on the FT64 Stream Processor
 Yu Deng, Xuejun Yang, Xiaobo Yan, Kun Zeng
 
 2 
  Memory Hierarchy Design (14:00~16:05)
 Session Chair : Sangyeun Cho (University of Pittsburgh)

 Exploring Data Tiling in SPM Allocation
 Lian Li, Hui Wu, Hui Feng, Jingling Xue

 Evolution of NAND Flash Memory Interface
 Sang Lyul Min, Eyee Hyun Nam, Young Hee Lee

 FCC-SDP: A Fast Close-Coupled Shared Data Pool for Multi-Core DSPs
 Dong Wang, Xiaowen Chen, Shuming Chen, Xing Fang, Shuwei Sun

 Exploiting Single-Usage for Effective Memory Management
 Thomas Piquet, Olivier Rochecouste, Andrą„e Seznec

 An Alternative Organization of Defect Map for Defect-Resilient Embedded On-Chip Memories
 Kang Yi, Shih-Yang Cheng, Young-Hwan Park, Fadi Kurdahi, Ahmed Eltawil
 
 3 
  Embedded System and Mobility Network (16:30~18:10 )
 Session Chair : Emre Ozer (ARM)

 An Effective Design of Master-Slave Operating System Architecture for Multiprocessor Embedded Systems
 Minyeol Seo, Ha Seok Kim, Ji Cjan Maeng, Jimin Kim, Minsoo Ryu

 Optimal Placement of Frequently Accessed IPs in Mesh NoCs
 Reza Moraveji, Hamid Sarbazi-Azad, Maghsoud Abbaspour

 An Efficient Link Controller for Test Access to IP Core-based Embedded System Chips
 Jaehoon Song, Hyunbean Yi, Juhee Han, Sungju Park

 Performance of Keyword Connection Algorithm in Nested Mobility Networks
 Sang-Hoon Ryu, Doo-Kwon Baik

DAY 3
Keynote

 Power-Efficient Heterogeneous Multicore Technology for Digital Convergence (9:00~10:00 )
 Kunio Uchiyama   [ Abstract ]   [ Bio ]
 
      4      
  Power and Temperature Awareness (10:25~12:30 )
 Session Chair : Sung Woo Chung (Korea University)

 Leakage Energy Reduction in Cache Memory by Software Self-Invalidation
 Kiyofumi Tanaka, Takenori Fujita

 Exploiting Task Temperature Profiling in Temperature-Aware Task Scheduling for Computational Clusters
 Daniel C. Vanderster, Amirali Baniasadi, Nikitas J. Dimopoulos

 Runtime Performance Projection Model for Dynamic Power Management
 Sang-Jeong Lee, Hae-Kag Lee, Pen-Chung Yew

 A Power-Aware Alternative for the Perceptron Branch Predictor
 Kaveh Aasaraai, Amirali Baniasadi

 Power Consumption and Performance Analysis of 3D NoCs
 Akbar Sharifi, Hamid Sarbazi-Azad
 
5
  Image Processing and Recognition (14:00~16:05 )
 Session Chair : Youngho Choi (Konkuk University)

 A Design Methodology for Performance-Resource Optimization of a Generalized 2D Convolution Architecture
 with Quadrant Symmetric Kernels

 Ming Z. Zhang, Vijayan K. Asari

 Bipartition Architecture for Low Power JPEG Huffman Decoder
 Shanq-Jang Ruan, Wei-Te Lin

 A SWP Specification for Sequential Image Processing Algorithms
 Wensheng Tang, Shaogang Wang, Dan Wu, Wangqiu Kuang

 A Stream System-on-Chip Architecture for High Speed Target Recognition based on Biologic Vision
 Nan Wu, Qianming Yang, Mei Wen,Yi He, Changqing Xun, Chunyuan Zhang

 FPGA-Accelerated Active Shape Model for Real-Time People Tracking
 Yong Dou, Jinbo Xu
 
6
  Multiprocessors and Multithreading I (16:30~18:10 )
 Session Chair : Rajeev Thakur (Argonne Nat'l Lab.)

 Performance Evaluation of Evolutionary Multi-core and Aggressively Multi-threaded Processor Architectures
 Partha Tirumalai, Yonghong Song, Spiros Kalogeropulos

 Synchronization Mechanisms on Modern Multi-Core Architecture
 Shaoshan Liu, Jean-Luc Gaudiot

 Concerning with On-Chip Network Features to Improve Cache Coherence Protocols for CMPs
 Hongbo Zeng, Kun Huang, Ming Wu, and Weiwu Hu

 Generalized Wormhole Switching: A New Fault-Tolerant Mathematical Model for Adaptively Wormhole-Routed
 Interconnect Networks

 F. Safaei, A. Khonsari, M. Fathy, N. Talebanfard, M. Ould-Khaoua

DAY 4
      7      
  Multiprocessors and Multithreading II (9:00~9:50 )
 Session Chair : Pen-Chung Yew (University of Minnesota)

 Open Issues in MPI Implementation
 Rajeev Thakur, William Gropp

 Implicit Transactional Memory in Kilo-Instruction Multiprocessors
 Marco Galluzzi, Enrique Vallejo, Adrian Cristal, Fernando Vallejo, Ramon Beivide, Per Stenstrom, James E. Smith, Mateo Valero
 
  Processor Core Design (10:20~12:00 )
 Session Chair : Colin Egan (University of Hertfordshire)

 Design of a Low-Power Embedded Processor Architecture Using Asynchronous Function Units
 Yong Li, Zhiying Wang, Xuemi Zhao, Jian Ruan, Kui Dai

 A Bypass Mechanism to Enhance Branch Predictor for SMT Processors
 Yongfeng Pan, Xiaoya Fan, Liqiang He, Deli Wang

 Thread Priority-Aware Random Replacement in TLBs for a High-Performance Real-time SMT Processor
 Emre Ozer, Stuart Biles

 Architectural Solution to Object-Oriented Programming
 Tan Yiyu, Anthony S. Fong, Yang Xiaojian


 

 

 

 

 

 

 

 

 

 

 

 

 

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